DAC38RF80 datasheet(49/155 Pages) TI1

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DAC38RF80, DAC38RF83, DAC38RF84

DAC38RF85, DAC38RF90, DAC38RF93

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SLASEA3C – DECEMBER 2016 – REVISED JULY 2017

DAC38RF83 DAC38RF93

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8.3.9 Multi-Device Synchronization

In many applications, such as multi antenna systems where the various transmit channels information is

correlated, it is required that the latency across the link is deterministic and multiple DAC devices are completely

synchronized such that their outputs are phase aligned. The DAC38RFxx achieves the deterministic latency

using SYSREF (JESD204B Subclass 1).

SYSREF is generated from the same clock domain as DACCLK. After having resynchronized its local multiframe

clock (LMFC) to SYSREF, the DAC will request a link re-initialization via SYNC interface. Processing of the

signal on the SYSREF input can be enabled and disabled via the SPI interface.

The SYSREF capture circuit and the timing requirements relative to device clock are described in SYSREF

Capture Circuit.

8.3.10 SYSREF Capture Circuit

The JESD204B standard for Device Subclass 1 introduces a SYSREF signal that can be used as a global timing

reference to align the phase of the internal local multiframe clock (LMFC) and frame clock across multiple

devices. This allows the system to achieve deterministic latency and align data samples across several data

converters. The SYSREF signal accomplishes this goal by identifying a device clock edge for each chip that can

be used as an alignment reference. In particular, the LMFC and frame clock align to the device clock edge upon

which the SYSREF transition from “0” to “1” is sampled. SYSREF may be periodic, one-shot, or “gapped”

periodic and its period must be a multiple of the LMFC period.

Figure 54. SYSREF Signal Timing

With high-speed device clocks, the phase of the SYSREF signals relative to the device clock must meet the

setup/hold time requirements of each individual device clock. Historically, this has been done by controlling the

board-level routing delay and/or employing commercial clock distribution capable of generating device clocks and

SYSREF signals with programmable delays and with the option of splitting SYSREF into multiple SYSREFS,

each with its own fine-tuned delay. Since the DAC38RFxx family supports device clock frequencies up to 9 GHz,

a SYSREF capture circuit is includes in the DAC38RFxx that allows a relaxation in meeting the device clock

setup and hold.

The SYSREF capture circuit provides:

•

tolerance to manufacturing and environmental variations in SYSREF phase

•

immunity to sampling errors due to setup/hold/meta-stability

•

information about phase of SYSREF relative to DAC clock inside the data converter

•

software compensation for phase misalignment due to PCB design errors

The concepts behind the SYSREF capture scheme are illustrated in Figure 55.

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