RT4801H

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is a registered trademark of Richtek Technology Corporation.

DS4801H-00

May

2016

www.richtek.com

9

I

Slave Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 = LSB

1

1

1

0

0

1

1

R/W

Write Command

(a) Write single byte of data to Register

1

1

1

0

0

1

1

0

Slave

ACK

Slave Address

Register Address

R7 R6

R3

R5 R4

R2 R1 R0 Slave

ACK

Data From Master

Start

Slave

ACK

Stop

D7 D6 D5 D4 D3 D2 D1 D0

(b) Write multiple bytes of data to Registers

1

1

1

0

0

1

1

0

Slave

ACK

Slave Address

Slave

ACK

Start

D7 D6 D5 D4 D3 D2 D1 D0 Slave

ACK

Slave

ACK

Stop

Last Data From Master

R7 R6

R3

R5 R4

R2 R1 R0

D7 D6 D5 D4 D3 D2 D1 D0

Slave

ACK

D7 D6 D5 D4 D3 D2 D1 D0

Read Command

(a) Read single byte of data from Register

1

1

1

0

0

1

1

0

Slave

ACK

Slave Address

Register Address

1

1

1

0

0

1

1

1

Slave

ACK

Slave Address

Data From Master

Re-

start

Start

Slave

ACK

D7 D6 D5 D4 D3 D2 D1 D0

Master

NACK

Stop

D7 D6 D5 D4 D3 D2 D1 D0

(b) Read multiple bytes of data from Registers

1

1

1

0

0

1

1

0

Slave

ACK

1

1

1

0

0

1

1

1

Slave

ACK

Slave Address

Master

ACK

Re-

start

Start

Slave Address

Register Address

Master

NACK

Stop

Last Data From Master

D7 D6 D5 D4 D3 D2 D1 D0

Slave

ACK

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

Start : Start command

R7 to R0 : Register Address.

VOP : Register address = 0X00h

VON : Register address = 0X01h

DISP : Register address = 0x03h

DISN : Register address = 0x03h

APPS : Register address = 0x03h

R/W : Read active (R/W = H) or Write active (R/W = L)

ACK : Acknowledge = L active

D7 to D0 : Write data when WRITE command or read

data when READ command

Stop : Stop command