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MPC7450EC 데이터시트(PDF) 13 Page - Motorola, Inc |
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MPC7450EC 데이터시트(HTML) 13 Page - Motorola, Inc |
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13 / 52 page ![]() MOTOROLA MPC7450 RISC Microprocessor Hardware Specifications 13 Electrical and Thermal Characteristics Table 6 provides the DC electrical characteristics for the MPC7450. Table 6. DC Electrical Specifications At recommended operating conditions. See Table 4. Characteristic Nominal Bus Voltage1 Symbol Min Max Unit Notes Input high voltage (all inputs except SYSCLK) 1.5 VIH GVDD × 0.65 GVDD + 0.3 V 6 1.8 VIH OVDD/GVDD × 0.65 OVDD/GVDD + 0.3 V 2.5 VIH 1.7 OVDD/GVDD + 0.3 V Input low voltage (all inputs except SYSCLK) 1.5 VIL –0.3 GVDD × 0.35 V 6 1.8 VIL –0.3 OVDD/GVDD × 0.35 V 2.5 VIL –0.3 0.7 V SYSCLK input high voltage — CVIH 1.4 OVDD + 0.3 V SYSCLK input low voltage — CVIL –0.3 0.4 V Input leakage current, Vin = GVDD/OVDD + 0.3 V —Iin — 10 µA 2, 3 High impedance (off-state) leakage current, Vin = GVDD/OVDD + 0.3 V —ITSI — 10 µA 2, 3, 5 Output high voltage, IOH = –5 mA 1.5 VOH OVDD/GVDD – 0.45 — V 6 1.8 VOH OVDD/GVDD – 0.45 — V 2.5 VOH 1.7 — V Output low voltage, IOL = 5 mA 1.5 VOL — 0.45 V 6 1.8 VOL — 0.45 V 2.5 VOL — 0.7 V Capacitance, Vin = 0 V, f = 1 MHz L3 interface — Cin — 9.5 pF 4 All other inputs — 8.0 pF 4 Notes: 1. Nominal voltages; see Table 4 for recommended operating conditions. 2. For processor bus signals, the reference is OVDD while GVDD is the reference for the L3 bus signals. 3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals. 4. Capacitance is periodically sampled rather than 100% tested. 5. The leakage is measured for nominal OVDD/GVDD and VDD, or both OVDD/GVDD and VDD must vary in the same direction (for example, both OVDD and VDD vary by either +5% or –5%). 6. Applicable to L3 bus interface only. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com AR CH IVE D B Y F RE ES CA LE SE MI CO ND UC TO R, INC . |
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