TNETX15AE datasheet(50/78 Pages) TI

50 / 78 page

TNETX15AE

ADDRESS-LOOKUP DEVICE

SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

x24C02 EEPROM interface

BYTE 3

BYTE 2

BYTE 1

BYTE 0

DIO

ADDRESS

SIO

Control

0x08

The flash EEPROM interface is provided so the system-level manufacturers can provide a preconfigured

system to their customers. Customers can change or reconfigure the system and retain preferences between

system power downs. The flash EEPROM contains configuration and initialization information that is accessed

infrequently (typically at power up and reset). The host can write to the EEPROM through this SIO

The TNETX15AE implements a two-wire serial interface, consisting of EDIO and EDCLK that communicates

with the EEPROM. Similar to the MII interface, the TNETX15AE does not implement any timing or data structure

on its serial interface. Appropriate timing and frame format must be ensured by the management software by

setting or clearing bits at the right times. There are no limits to the size or organization of the EEPROM when

the host is driving this interface, but these same terminals are used by an internal state machine to load the

contents of the EEPROM into internal registers. This state machine expects a 24C02 (as device 0) on the serial

bus. Refer to the manufacturer’s data sheet for a description of the EEPROM waveforms.

If an EEPROM is not installed, EDIO should be tied low. For EEPROM operation, EDIO and EDCLK require an

external pullup (see EEPROM data sheet). The TNETX15AE detects the presence or absence of the EEPROM

and indicates this in the NEEPM bit of the control register.

initialization

The TNETX15AE can be designed for stand-alone use, with no need for a management CPU. It can be reset

and initialized with or without a host CPU. This section discusses the steps necessary to bring the TNETX15AE

up to an operating level.

TNETX3150/TNETX3150A/TNETX3100 initialization

If multiple-port EAM codings are used, then TNETX3150/TNETX3150A/TNETX3100 IOBMOD bit in the systcl

must

set

reversed

(IOBMOD

TNETX3150/TNETX3150A/TNETX3100

systcl register = 0), the ability to send frames to multiple ports, but not all ports, is lost. Multicasts become

broadcasts to all ports, regardless of EAM code. Also, the broadcast is not in order with other traffic on each

transmit queue.

The user also must disable the TNETX3150/TNETX3150A/TNETX3100 internal-address matching when using

the TNETX15AE. This is accomplished by writing a 1 to the ADRDIS bit in the port control register of each port.

resetting the TNETX15AE

hardware reset

The TNETX15AE is hardware reset by asserting RESET low. The TNETX15AE comes out of reset when RESET

goes high.

During a hardware reset, no access to the internal registers is allowed. A read or write stalls, that is, SRDY does

not come true until the hardware state machine is done. All access registers and internal registers are initialized

to default values. Hardware reset should complete in a few tens of clock cycles.

If an EEPROM is detected (after a hardware reset), the TNETX15AE begins the EEPROM auto-loading

process. No DIO operations are allowed during auto-loading.

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