| 전자부품 데이터시트 검색엔진 |
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S8249 데이터시트(PDF) 13 Page - Seiko Instruments Inc |
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S8249 데이터시트(HTML) 13 Page - Seiko Instruments Inc |
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13 / 23 page ![]() VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.4_00 S-8249 Series 13 5. DP pin The S-8249 Series has the DP pin (Test mode switching pin). The S-8249 Series is set to test mode (used to shorten the delay time) by inputting a voltage of VDPH or higher to the DP pin. Table 13 DP Pin Status Open (VDP = VSS) Normal operation mode "H" (VDP ≥ VDPH) Test mode "L" (VDP ≤ VDPL) Normal operation mode In test mode, the cell balancing detection delay time (tBU) and overcharge detection delay time (tCU) are shortened to 1/64 of the delay time in the normal operation mode. The DP pin is pulled down to VSS by the internal resistor. When in a mode other than test mode, leave the DP pin open or short it with VSS. |
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