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WM8602SEDS/RV 데이터시트(PDF) 20 Page - Wolfson Microelectronics plc |
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WM8602SEDS/RV 데이터시트(HTML) 20 Page - Wolfson Microelectronics plc |
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20 / 46 page ![]() WM8602 Product Preview w PP Rev 1.5 May 2004 20 MCLK / XIN AUDIO SAMPLE RATE SR [3:0] (MPEG = 0) CLKDIV2=0 CLKDIV2=1 [MHz] [MHz] [kHz] 32 (MCLK/384) 0001 12.288 24.576 48 (MCLK/256) 0000 96 (MCLK/256) 0011 24.576 49.152 192 (MCLK/128) 0010 11.2896 22.5792 44.1 (MCLK/256) 0100 88.2 (MCLK/256) 0111 22.5792 45.1584 176.4 (MCLK/128) 0110 32 (MCLK/512) 1001 18.432 36.864 48 (MCLK/384) 1000 96 (MCLK/384) 1011 36.864 not supported 192 (MCLK/192) 1010 16.9344 33.8688 44.1 (MCLK/384) 1100 88.2 (MCLK/384) 1111 33.8688 not supported 176.4 (MCLK/192) 1110 (MPEG = 1) 32 0001 44.1 0100 48 0000 88.2 0111 96 0011 176.4 0110 27.000 not supported 192 0010 Table 14 Master Clock and Sample Rates The following Figure 14, Figure 15, Figure 16 and Figure 17 illustrate the different Clocking and Audio IF modes. Figure 14 Clock and Audio IF: Clock Master / Audio IF Slave (Default) |
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