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Z85233 데이터시트(PDF) 21 Page - Zilog, Inc.

부품명 Z85233
상세설명  The Zilog SCC Serial Communication Controller
PDF  317 Pages
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제조업체  ZILOG [Zilog, Inc.]
홈페이지  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z85233 데이터시트(HTML) 21 Page - Zilog, Inc.

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SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2-2
2.2 Z80X30 INTERFACE TIMING (Continued)
2.2.1 Z80X30 Read Cycle Timing
The read cycle timing for the Z80X30 is shown in Figure 2-1.
The register address on AD7-AD0, as well as the state of
/CS0 and /INTACK, are latched by the rising edge of /AS.
R//W must be High before /DS falls to indicate a read
cycle. The Z80X30 data bus drivers are enabled while CS1
is High and /DS is Low.
Figure 2-1. Z80X30 Read Cycle
/AS
/CS0
/INTACK
AD7 - AD0
R//W
CS1
/DS
Address
Data Valid
UM010901-0601



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