68HC908RF datasheet(73/188 Pages) MOTOROLA

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Internal Clock Generator Module (ICG)

Functional Description

MC68HC908RF2 — Rev. 4.0

Data Sheet

MOTOROLA

Internal Clock Generator Module (ICG)

the low-frequency base clock (IBASE) is used in place of ICLK because it always

operates at or near 307.2 kHz. For proper operation, EREF must be at least twice

as slow as IBASE and IREF must be at least twice as slow as ECLK.

To guarantee that IREF is slower than ECLK and EREF is slower than IBASE, one

of the signals is divided down. Which signal is divided and by how much is

determined by the external slow (EXTSLOW) bit in the configuration register,

according to the rules in Table 6-2. Note that each signal (IBASE and ECLK) is

always divided by four. A longer divider is used on either IBASE or ECLK based on

the EXTSLOW bit.

NOTE:

If EXTSLOW is not set according to the rules defined in Table 6-2, the clock

monitor could switch clock sources unexpectedly.

The long divider (divide by 4096) is also used as an external crystal stabilization

divider. The divider is reset when the external clock generator is off (ECGEN is

clear). When the external clock generator is first turned on, the external clock

generator stable bit (ECGS) will be clear. This condition automatically selects

ECLK as the input to the long divider. The external stabilization clock (ESTBCLK)

will be ECLK divided by 4096. This timeout allows the crystal to stabilize. The falling

edge of ESTBCLK is used to set ECGS. (ECGS will set after a full 16 or 4096

cycles.) When ECGS is set, the divider returns to its normal function. ESTBCLK

may be generated by either IBASE or ECLK, but any clocking will reinforce only the

set condition. If ECGS is cleared because the clock monitor determined that ECLK

was inactive, the divider will revert to a stabilization divider. Since this will change

the EREF and IREF divide ratios, it is important to turn the clock monitor off

(CMON = 0) after inactivity is detected to ensure valid recovery.

Table 6-2. Clock Monitor Reference Divider Ratios

ICGON ECGON ECGS EXTSLOW

External

Frequency

EREF

Divider

Ratio

EREF

Frequency

ESTBCLK

Divider

Ratio

ESTBCLK

Frequency

IREF

Divider

Ratio

IREF

Frequency

Off

0Off

Min 30 kHz

Off

4096

(ECLK)

1.875 kHz

1*4

76.8 kHz

±25%

Max 8 MHz

500 kHz

Min 1 MHz

128*4

1.953 kHz

4096

(ECLK)

244 Hz

1*4

76.8 kHz

±25%

Max 8 MHz

15.63 kHz

1.953 kHz

Min 30 kHz

1*4

7.5 kHz

4096

(IBASE)

75 Hz

±25%

16*4

4.8 kHz

±25%

Max 100 kHz

25.0 kHz

U: Unaffected. Refer to section of table where ICGON or ECGON is set to x (don’t care).

IBASE is always used as the internal frequency (307.2 kHz).

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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