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91C100FDREVB 데이터시트(PDF) 22 Page - SMSC Corporation

부품명 91C100FDREVB
상세설명  FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY
PDF  68 Pages
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제조업체  SMSC [SMSC Corporation]
홈페이지  http://www.smsc.com
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91C100FDREVB 데이터시트(HTML) 22 Page - SMSC Corporation

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SMSC DS – LAN91C100FD REV. B
Page 22
Rev. 05/31/2000
BANK 0
OFFSET
NAME
TYPE
SYMBOL
4
RECEIVE CONTROL REGISTER
READ/WRITE
RCR
HIGH
BYTE
SOFT
RST
FILT
CAR
ABORT_
ENB
0
Reserved
Reserved
STRIP
CRC
RXEN
0
0
0
0
0
0
0
0
LOW
BYTE
Reserved
Reserved
Reserved
Reserved
Reserved
ALMUL
PRMS
RX_
ABORT
0
0
0
0
0
0
0
0
SOFT_RST - Software-Activated Reset. Active high. Initiated by writing this bit high and terminated by writing the bit low.
The LAN91C100FD’s configuration is not preserved except for Configuration, Base, and IA0-IA5 Registers. EEPROM is
not reloaded after software reset.
FILT_CAR - Filter Carrier. When set filters leading edge of carrier sense for 12 bit times (3 nibble times). Otherwise
recognizes a receive frame as soon as carrier sense is active. (Does NOT filter RX DV on MII!)
ABORT_ENB - Enables abort of receive when collision occurs. Defaults low. When set, the LAN91C100FD will
automatically abort a packet being received when the appropriate collision input is activated (COL100 for MII, COL for non-
MII). This bit has no effect if the SWFDUP bit in the TCR is set.
STRIP_CRC - When set it strips the CRC on received frames. When clear the CRC is stored in memory following the
packet. Defaults low.
RXEN - Enables the receiver when set. If cleared, completes receiving current frame and then goes idle. Defaults low on
reset.
ALMUL - When set accepts all multicast frames (frames in which the first bit of DA is '1'). When clear accepts only the
multicast frames that match the multicast table setting. Defaults low.
PRMS - Promiscuous mode. When set receives all frames. Does not receive its own transmission unless it is in Full
Duplex!
RX_ABORT - This bit is set if a receive frame was aborted due to length longer than 2K bytes. The frame will not be
received. The bit is cleared by RESET or by the CPU writing it low.
Reserved - Must be 0.



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