80960JD datasheet(54/59 Pages) INTEL

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80960JD

PRODUCT PREVIEW

Table 21. Summary of

n-Word Load and Store Accesses (n = 1, 2, 3, 4)

Address Offset

from Natural

Boundary in Bytes

Accesses on 8-Bit Bus

(WIDTH1:0=00)

Accesses on 16 Bit Bus

(WIDTH1:0=01)

Accesses on 32 Bit

Bus (WIDTH1:0=10)

+0 (aligned)

(

n =1, 2, 3, 4)

•

n burst(s) of 4 bytes

•

case

n=1:

burst of 2 short words

•

case

n=2:

burst of 4 short words

•

case

n=3:

burst of 4 short words

burst of 2 short words

•

case

n=4:

2 bursts of 4 short words

•

burst of

n word(s)

+1 (

n =1, 2, 3, 4)

+5 (

n = 2, 3, 4)

+9 (

n = 3, 4)

+13 (

n = 3, 4)

• byte access

• burst of 2 bytes

•

n-1 burst(s) of 4 bytes

• byte access

• short-word access

•

n-1 burst(s) of 2 short words

• byte access

• short-word access

•

n-1 word access(es)

• byte access

+2 (

n =1, 2, 3, 4)

+6 (

n = 2, 3, 4)

+10 (

n = 3, 4)

+14 (

n = 3, 4)

• burst of 2 bytes

•

n-1 burst(s) of 4 bytes

• burst of 2 bytes

• short-word access

•

n-1 burst(s) of 2 short words

• short-word access

•

n-1 word access(es)

• short-word access

+3 (

n =1, 2, 3, 4)

+7 (

n = 2, 3, 4)

+11 (

n = 3, 4)

+15 (

n = 3, 4)

• byte access

•

n-1 burst(s) of 4 bytes

• burst of 2 bytes

• byte access

•

n-1 burst(s) of 2 short words

• short-word access

• byte access

•

n-1 word access(es)

• short-word access

• byte access

+4 (

n = 2, 3, 4)

+8 (

n = 3, 4)

+12 (

n = 3, 4)

•

n burst(s) of 4 bytes

•

n burst(s) of 2 short words

•

n word access(es)

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