ECT25S40 datasheet(17/46 Pages) E-CMOS

17 / 46 page

E-CMOS Corp. (www.ecmos.com.tw)

Page 17 of 46

4L08N-Rev.F001

ECT25S40

4M BIT SPI NOR FLASH

Figure 7. Read Status Register Sequence Diagram

Write Status Register (01H)

See Figure 8, the Write Status Register instruction allows new values to be written to the

Status Register.Before it can be accepted, a Write Enable instruction must previously have

Been executed. After the Write Enable instruction has been decoded and executed, the device

sets the Write Enable Latch (WEL).

The Write Status Register instruction has no effect on S15, S1 and S0 of the Status Register.

/CS must be driven high after the eighth or sixteen bit of the data byte has been latched in. If

not, the Write Status Register instruction is not executed. If /CS is driven high after eighth bit

of the data byte, the CMP and QE and SRP1 bits will be cleared to 0. As soon as /CS is

driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated.

While the Write Status Register cycle is in progress, the Status Register may still be read to

check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during

the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is

completed, the Write Enable Latch is reset.

The Write Status Register instruction allows the user to change the values of the Block

Protect (SEC, TB, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as

read-only, as defined in Table 3. The Write Status Register instruction also allows the user to

set or reset he Status Register Protect (SRP1 and SRP0) bits in accordance with the Write

Protect (/WP) signal.The Status Register Protect (SRP1 and SRP0) bits and Write Protect

(/WP) signal allow the device to be put in the Hardware Protected Mode. The Write Status

Figure 8. Write Status Register Sequence Diagram

ECT25S40 데이터시트(PDF) 17 Page - E-CMOS Corporation