Page 18 of 45

5B16N-Rev.F001

ECT25S80

8M BIT SPI NOR FLASH

Write Enable for Volatile Status Register (50H)

See Figure 9, the non-volatile Status Register bits can also be written to as volatile bits. During power up reset,

the non-volatile Status Register bits are copied to a volatile version of the Status Register that is used during

device operation. This gives more flexibility to change the System configuration and memory protection

schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the

Status Register non-volatile bits. To write the volatile version of the Status Register bits, the Write Enable for

Volatile Status Register(50h) instruction must be issued prior to each Write Status Registers (01h) instruction.

Write Enable for Volatile Status Register instruction will not set the Write Enable Latch bit, it is only valid for the

next following Write Status Registers instruction, to change the volatile Status Register bit values.

Figure 9. Write Enable for Volatile Status Register

Read Instructions

Read Data (03H)

See Figure 10, the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit

being latched-in during the rising edge of SCLK. Then the memory content, at

that address, is shifted out on

SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The address is

automatically incremented to the next higher address

after each byte of data is shifted out allowing for a

continuous stream of data. This means

that the entire memory can be accessed with a single command as

long as the clock continues. The command is completed by driving /CS high. The whole memory can be read

with a

single Read Data Bytes (READ) instruction. Any Read Data Bytes (READ) instruction, while

an Erase,

Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Normal read mode running up to 50MHz.

Figure 10. Read Data Bytes Sequence Diagram