ECT25S40LP1CR datasheet(30/46 Pages) E-CMOS

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E-CMOS Corp. (www.ecmos.com.tw)

Page 30 of 46

4L08N-Rev.F001

ECT25S40

4M BIT SPI NOR FLASH

Figure 25. Erase Security Registers instruction Sequence Diagram

Program Security Registers (42H)

See Figure 26,

the Program Security Registers instruction is similar to the Page Program

instruction. It allows from 1 to 256 bytes Security Registers data to be programmed. A Write

Enable instruction must previously have been executed to set the Write Enable Latch bit

Before sending the Program Security Registers instruction. The Program Security Registers

instruction is entered by driving /CS Low, followed by the instruction code(42H),3-byte

address and at least one data byte on SI. As soon as /CS is driven high, the self-timed

Program Security Registers cycle (whose duration

tPP)

initiated.While the Program

Security Registers cycle is in progress, the Status Register may be read to check the value of

the Write In Progress (WIP) bit.The Write In Progress (WIP) bit is 1 during the self-timed

Program Security Registers cycle, and is 0 when it is completed. At some unspecified time

before the cycle is completed, the Write Enable Latch bit is reset.

If the Security Registers Lock Bit (LB3/LB2/LB1) is set to 1, the Security Registers will be

permanently locked. Program Security Registers instruction will be ignored.

Figure 26. Program Security Registers instruction Sequence Diagram

Address

A23-A16

A15-A8

A7-A0

Security Registers 1

00H

01H

Byte Address

Security Registers 2

00H

02H

Byte Address

Security Registers 3

00H

03H

Byte Address

ECT25S40LP1CR 데이터시트(PDF) 30 Page - E-CMOS Corporation