| 전자부품 데이터시트 검색엔진 |
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LH0101 데이터시트(PDF) 7 Page - National Semiconductor (TI) |
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LH0101 데이터시트(HTML) 7 Page - National Semiconductor (TI) |
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7 / 12 page ![]() Application Hints (Continued) Thermal Resistance The thermal resistance between two points of a conductive system is expressed as i12 e T1 b T2 PD CW where subscript order indicates the direction of heat flow A simplified heat transfer circuit for a cased semiconductor and heat sink system is shown in the figure below The circuit is valid only if the system is in thermal equilibrium (constant heat flow) and there are indeed single specific temperatures TJ TC and TS (no temperature distribution in junction case or heat sink) Nevertheless this is a reason- able approximation of actual performance TLK5558 – 8 FIGURE 2 Semiconductor-Heat Sink Thermal Circuit The junction-to-case thermal resistance iJC specified in the data sheet depends upon the material and size of the pack- age die size and thickness and quality of the die bond to the case or lead frame The case-to-heat sink thermal re- sistance iCS depends on the mounting of the device to the heat sink and upon the area and quality of the contact sur- face Typical iCS for a TO-3 package is 05 to 07 CW and 03 to 05 CW using silicone grease The heat sink to ambient thermal resistance iSA depends on the quality of the heat sink and the ambient conditions Cooling is normally required to maintain the worst case op- erating junction temperature TJ of the device below the specified maximum value TJ(MAX) TJ can be calculated from known operating conditions Rewriting the above equa- tion we find iJA e TJ b TA PD CW TJ e TA a PDiJA C Where PD (VS b VOUT)IOUT a lVab (Vb)lIQ for a DC Signal iJA e iJC a iCS a iSA and VS e Supply Voltage iJC for the LH0101 is about 2 CW Stability and Compensation As with most amplifiers care should be taken with lead dress component placement and supply decoupling in or- der to ensure stability For example resistors from the out- put to an input should be placed with the body close to the input to minimize ‘‘pickup’’ and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground A feedback pole is created when the feedback around any amplifier is resistive The parallel resistance and capaci- tance from the input device (usually the inverting input) to ac ground set the frequency of the pole In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin However if the feedback pole is less than approximately six times the ex- pected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp The value of the added capacitor should be such that the RC time consistant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant Some inductive loads may cause output stage oscillation A 01 mF ceramic capacitor in series with a 10X resistor from the output to ground will usually remedy this situation TLK5558 – 9 FIGURE 3 Driving Inductive Loads Capacitive loads may be compensated for by traditional techniques (See ‘‘Operational Amplifiers Theory and Prac- tice’’ by Roberge published by Wiley) TLK5558 – 10 FIGURE 4 RC and CC Selected to Compensate for Capacitive Load A similar but alternative technique may be used for the LH0101 TLK5558 – 11 FIGURE 5 Alternate Compensation for Capacitive Load 7 |
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