AD4010 datasheet(21/36 Pages) AD

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Preliminary Technical Data

AD4002/AD4006/AD4010

Rev. PrA | Page 21 of 36

DRIVER AMPLIFIER CHOICE

Although the AD4002/AD4006/AD4010 are easy to drive, the

driver amplifier must meet the following requirements:

•

The noise generated by the driver amplifier must be kept

low enough to preserve the SNR and transition noise

performance of the AD4002/AD4006/AD4010. The noise

from the driver is filtered by the single-pole, low-pass filter

of the analog input circuit made by RIN and CIN, or by the

external filter, if one is used. Because the typical noise of the

AD4002/AD4006/AD4010 is 30 µV rms, the SNR

degradation due to the amplifier is

(

)

(

)

(

) 













−

μV

log

LOSS

SNR

where:

f−3 dB is the input bandwidth, in megahertz, of the AD4002/

AD4006/AD4010 (10 MHz) or the cutoff frequency of the input

filter, if one is used.

N is the noise gain of the amplifier (for example, 1 in buffer

configuration).

eN is the equivalent input noise voltage of the op amp, in

nV/√Hz.

•

For ac applications, the driver must have a THD performance

commensurate with the AD4002/AD4006/AD4010.

•

For multichannel multiplexed applications, the driver

amplifier and the analog input circuit of the AD4002/

AD4006/AD4010 must settle for a full-scale step onto the

capacitor array at an 18-bit level (0.000191%, 1.91 ppm). In

the data sheet of the amplifier, settling at 0.1% to 0.01% is

more commonly specified. This settling may differ

significantly from the settling time at an 18-bit level and

must be verified prior to driver selection.

High Frequency Input Signals

The AD4002/AD4006/AD4010 ac performance over a wide

input frequency range using a 5 V reference voltage is shown

in Figure 36 and Figure 37. Unlike other traditional SAR ADCs,

the AD4002/AD4006/AD4010 maintain exceptional ac perfor-

mance for input frequencies up to the Nyquist frequency with

minimal performance degradation. Note that the input frequency

is limited to the Nyquist frequency of the sample rate in use.

TBD

Figure 36. SNR, SINAD, and ENOB vs. Input Frequency, VDD = 1.8 V,

VIO = 3.3 V, VREF = 5 V, 25°C

TBD

Figure 37. THD and SFDR vs. Input Frequency, VDD = 1.8 V, VIO = 3.3 V,

VREF = 5 V, 25°C Multiplexed Applications

The AD4002/AD4006/AD4010 significantly reduce system

complexity and cost for multiplexed applications that require

superior performance in terms of noise, power, and throughput.

Figure 38 shows a simplified block diagram of a multiplexed

data acquisition system including a multiplexer, an ADC driver,

and the precision SAR ADC.

SAR ADC

ADC

DRIVER

MULTIPLEXER

Figure 38. Multiplexed Data Acquisition Signal Chain Using the

AD4002/AD4006/AD4010

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