AD7617

Data Sheet

Rev. 0 | Page 42 of 51

ADDRESSING REGISTERS

The seven MSBs written to the device are decoded to determine which register is addressed. The seven MSBs consist of the register address

(REGADDR), Bits[5:0], and the read/write bit. The register address bits determine which on-chip register is selected. The read/write bit

determines if the remaining nine bits of data on the DB10/SDI lines are loaded into the addressed register. If the read/write bit is 1, the

bits load into the register addressed by the register select bits. If the read/write bit is 0, the command is seen as a read request. The addressed

register data is available to be read during the next read operation.

MSB

LSB

D15

D14

D13 to D9

D8 to D0

W/R

REGADDR, Bit 5

REGADDR, Bits[4:0]

DATA, Bits[8:0]

Table 21. Bit Descriptions for the Addressing Registers

Bits

Mnemonic

Description

D15

W/R

If a 1 is written to this bit, Bits[D8:D0] of this register are written to the register specified by REGADDR,

Bits[5:0]. Alternatively, if a 0 is written, the next operation is a read from the designated register.

D14

REGADDR, Bit 5

If a 1 is written to this bit, the contents of REGADDR, Bits[4:0] specifies the 32 sequencer stack registers.

Alternatively, if a 0 is written to this bit, a register is selected as defined by REGADDR, Bits[4:0].

[D13:D9]

REGADDR,

Bits[4:0]

When W/R = 1, the contents of REGADDR, Bits[4:0] determine register for selection as follows:

00001: reserved.

00010: selects the configuration register.

00011: selects the channel register.

00100: selects Input Range Register A1.

00101: selects Input Range Register A2.

00110: selects Input Range Register B1.

00111: selects Input Range Register B2.

01000: selects the status register

When W/R = 0 and REGADDR, Bits[4:0] contains 00000, the conversion codes are read.

[D8:D0]

DATA, Bits[8:0]

These bits are written into the corresponding register specified by REGADDR, Bits[5:0]. See the following

sections for detailed descriptions of each register.