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AD9680 데이터시트(PDF) 63 Page - Analog Devices

부품명 AD9680
상세설명  Dual Analog-to-Digital Converter
PDF  99 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD9680 데이터시트(HTML) 63 Page - Analog Devices

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Data Sheet
AD9680
Rev. C | Page 61 of 97
DDC EXAMPLE CONFIGURATIONS
Table 23 describes the register settings for multiple DDC example configurations.
Table 23. DDC Example Configurations
Chip
Application
Layer
Chip
Decimation
Ratio
DDC
Input
Type
DDC
Output
Type
Bandwidth
per DDC1
No. of Virtual
Converters
Required
Register Settings2
One DDC
2
Complex
Complex
38.5% × fS
2
Register 0x200 = 0x01 (one DDC; I/Q selected)
Register 0x201 = 0x01 (chip decimate by 2)
Register 0x310 = 0x83 (complex mixer; 0 dB gain; variable IF;
complex outputs; HB1 filter)
Register 0x311 = 0x04 (DDC I input = ADC Channel A;
DDC Q input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320, Register 0x321 =
FTW and POW set as required by application for DDC 0
Two DDCs
4
Complex
Complex
19.25% × fS
4
Register 0x200 = 0x02 (two DDCs; I/Q selected)
Register 0x201 = 0x02 (chip decimate by 4)
Register 0x310, Register 0x330 = 0x80 (complex mixer; 0 dB
gain; variable IF; complex outputs; HB2 + HB1 filters)
Register 0x311, Register 0x331 = 0x04 (DDC I input =
ADC Channel A; DDC Q input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320, Register 0x321 =
FTW and POW set as required by application for DDC 0
Register 0x334, Register 0x335, Register 0x340, Register 0x341 =
FTW and POW set as required by application for DDC 1
Two DDCs
4
Complex
Real
9.63% × fS
2
Register 0x200 = 0x22 (two DDCs; I only selected)
Register 0x201 = 0x02 (chip decimate by 4)
Register 0x310, Register 0x330 = 0x89 (complex mixer; 0 dB
gain; variable IF; real output; HB3 + HB2 + HB1 filters)
Register 0x311, Register 0x331 = 0x04 (DDC I Input = ADC
Channel A; DDC Q Input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320, Register 0x321 =
FTW and POW set as required by application for DDC 0
Register 0x334, Register 0x335, Register 0x340, Register 0x341 =
FTW and POW set as required by application for DDC 1
Two DDCs
4
Real
Real
9.63% × fS
2
Register 0x200 = 0x22 (two DDCs; I only selected)
Register 0x201 = 0x02 (chip decimate by 4)
Register 0x310, Register 0x330 = 0x49 (real mixer; 6 dB gain;
variable IF; real output; HB3 + HB2 + HB1 filters)
Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A;
DDC 0 Q input = ADC Channel A)
Register 0x331 = 0x05 (DDC 1 I input = ADC Channel B;
DDC 1 Q input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320, Register 0x321 =
FTW and POW set as required by application for DDC 0
Register 0x334, Register 0x335, Register 0x340, Register 0x341 =
FTW and POW set as required by application for DDC 1
Two DDCs
4
Real
Complex
19.25% × fS
4
Register 0x200 = 0x02 (two DDCs; I/Q selected)
Register 0x201 = 0x02 (chip decimate by 4)
Register 0x310, Register 0x330 = 0x40 (real mixer; 6 dB gain;
variable IF; complex output; HB2 + HB1 filters)
Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A;
DDC 0 Q input = ADC Channel A)
Register 0x331 = 0x05 (DDC 1 I input = ADC Channel B;
DDC 1 Q input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320, Register 0x321 =
FTW and POW set as required by application for DDC 0
Register 0x334, Register 0x335, Register 0x340, Register 0x341 =
FTW and POW set as required by application for DDC 1



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