AD7989-5BCPZ-R2 datasheet(13/24 Pages) AD

13 / 24 page

Data Sheet

AD7989-1/AD7989-5

Rev. B | Page 13 of 24

THEORY OF OPERATION

Figure 24. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7989-1/AD7989-5 are high speed, low power, single-

supply, precise, 18-bit ADCs using a successive approximation

architecture.

The AD7989-1 is capable of converting 100,000 samples per second

(100 kSPS), whereas the AD7989-5 is capable of converting 500,000

samples per second (500 kSPS), and they power down between

conversions. When operating at 100 kSPS, the ADC typically

consumes 700 µW, making the AD7989-1 ideal for battery-

powered applications.

The AD7989-1/AD7989-5 provide the user with an on-chip

track-and-hold amplifier and do not exhibit any pipeline delay

or latency, making these devices ideal for multiple multiplexed

channel applications.

The AD7989-1/AD7989-5 can be interfaced to any 1.8 V to 5 V

digital logic family. It is available in a 10-lead MSOP or a tiny

10 lead LFCSP that allows space savings and flexible configurations.

CONVERTER OPERATION

The AD7989-1/AD7989-5 are asuccessive approximation ADCs

based on a charge redistribution digital-to-analog converter (DAC).

Figure 24 shows the simplified schematic of the ADC. The

capacitive DAC consists of two identical arrays of 18 binary

weighted capacitors, which are connected to the twocomparator

inputs.

During the acquisition phase, terminals of the array tied to the

input of the comparator are connected toGND via Switch SW+

and Switch SW−. All independent switches are connected tothe

analog inputs. Therefore, the capacitor arrays are used as sampling

capacitors and acquire the analog signal on the IN+ input and IN−

input. When the acquisition phase completes and the CNV input

goes high, a conversion phase initiates. When the conversion phase

begins, SW+ and SW− are opened first. The two capacitor arrays

then disconnect fromthe inputs and connect to the GND input.

Therefore, the differentialvoltage between the IN+ and IN− inputs

captured at the end of the acquisition phase is applied to the

comparator inputs, causing the comparator to become unbalanced.

By switching each element of the capacitor array between GND

and REF, the comparator input varies bybinary weighted voltage

steps (VREF/2, VREF/4 ... VREF/262,144). The control logic toggles

these switches, starting with the MSB, to bring the comparator back

into a balanced condition. After the completion of this process, the

device returns tothe acquisition phase, and the control logic

generates the ADC output code.

Because the AD7989-1/AD7989-5 have an on-board conversion

clock, the serial clock, SCK, is not required for the conversion

process.

COMP

CONTROL

LOGIC

SWITCHES CONTROL

BUSY

OUTPUT CODE

CNV

65,536C

131,072C

LSB

SW+

MSB

LSB

SW–

MSB

65,536C

131,072C

IN+

REF

GND

IN–

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