13

PC107A [Preliminary]

2137C–HIREL–03/04

Figure 3 shows the supply voltage sequencing and separation cautions.

Figure 3. Supply Voltage Sequencing and Separation Cautions

Notes:

1. Numbers associated with waveform separations correspond to caution numbers listed in Table 3, “Recommended Operating

Conditions,” on page 12.

2. Refer to “Power Supply Voltage Sequencing” on page 42 for additional information.

3. Refer to Table 10 on page 25 for additional information on PLL Relock and reset signal assertion timing requirements.

4. Refer to Table 11 on page 26 for additional information on reset configuration pin setup timing requirements.

5. HRESET must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN clock cycle for the device to be in the

non-reset state.

OVDD/BVDD/GVDD(LVDD at 3.3V ----)

VDD/AVDD/LAVDD

LVDD at 5V

Time

3.3V

5V

2.5V

0

6

9

8

8

9

5.7

Voltage

Regulator

Delay(2)

Reset

Configuration Pins

HRESET

asserted 255

external memory

Clock cycles(3)

9 external memory

clock cycles setup time(4)

HRESET_CPU

HRESET

Vdd Stable

See Note 1 below.

VM = 1.4V

VM = 1.4V

Maximum rise time must be less than

one external memory clock cycle(5)

100

µs

PLL

Relock

Time(3)

Power Supply Ramp Up(2)

6