TAS3001CPWR datasheet(16/56 Pages) TI

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2−2

2.1.1

I2S Serial Format

The following are characteristics of this protocol:

•

LRCLK is the left/right clock. The left channel is transmitted when LRCLK is low. The right channel is

transmitted when LRCLK is high.

•

SDIN is sampled with the rising edge of SCLK.

•

SDOUT is transmitted on the falling edge of SCLK.

•

LRCK must have a 50% duty cycle.

MSB

SDIN

SCLK

MSB

LSB

MSB

LSB

Left Channel

Right Channel

SDOUT

LRCLK = fs

Figure 2−1. I2S-Compatible Serial Format

2.1.1.1 I2S Signal Timing

PARAMETER

MIN

TYP

MAX

UNIT

tc(SCLK)

SCLK frequency

6.144

MHz

td(SLR)

SCLK rising to LRCLK edge

td(SDOUT)

SDOUT valid from SCLK falling (see Note 1)

1/(256

× fs) +10

tsu(SDIN)

SDIN setup before SCLK rising edge

th(SDIN)

SDIN hold after SCLK rising edge

100

LRCLK

44.1/48

kHz

Duty cycle

50%

NOTE 1: Maximum of 50-pF external load on SDOUT.

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