Data Sheet

AD9467

Rev. D | Page 27 of 32

DON’T CARE

DON’T CARE

DON’T CARE

DON’T CARE

SDIO

SCLK

CSB

R/W

W1

W0

A12

A11

A10

A9

A8

A7

D5

D4

D3

D2

D1

D0

Figure 68. Serial Timing Details

Table 12. Serial Timing Definitions

Parameter

Timing (Minimum, ns)

Description

5

Setup time between the data and the rising edge of SCLK

2

Hold time between the data and the rising edge of SCLK

40

Period of the clock

5

Setup time between CSB and SCLK

2

Hold time between CSB and SCLK

16

Minimum period that SCLK should be in a logic high state

16

Minimum period that SCLK should be in a logic low state

10

Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK

falling edge (not shown in Figure 68)

10

Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising

edge (not shown in Figure 68)