AD9633 datasheet(13/42 Pages) AD

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AD9633

Data Sheet

Rev. B | Page 12 of 41

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VIN+A

VIN–A

AVDD

PDWN

CSB

SDIO/OLM

SCLK/DTP

D0+D

D0–D

D1+D

D1–D

DRVDD

AVDD

CLK+

CLK–

AVDD

VIN–D

VIN+D

DRVDD

D0+A

D0–A

D1+A

D1–A

AD9633

TOP VIEW

(Not to Scale)

NOTES

1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE

PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART.

THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR

PROPER OPERATION.

Figure 9. 48-Lead LFCSP Pin Configuration, Top View

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Description

AGND,

Exposed Pad

Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides

the analog ground for the part. This exposed pad must be connected to ground for proper

operation.

VIN+D

ADC D Analog Input True.

VIN−D

ADC D Analog Input Complement.

3, 4, 7, 34, 39, 45, 46

AVDD

1.8 V Analog Supply Pins.

5, 6

CLK−, CLK+

Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.

8, 29

DRVDD

Digital Output Driver Supply.

9, 10

D1−D, D1+D

Channel D Digital Outputs, (Disabled in One-Lane Mode1).

11, 12

D0−D, D0+D

Channel D Digital Outputs, (Disabled in One-Lane Mode1).

13, 14

D1−C, D1+C

Channel C Digital Outputs, (Channel D Digital Outputs in One-Lane Mode1).

15, 16

D0−C, D0+C

Channel C Digital Outputs.

17, 18

DCO−, DCO+

Data Clock Outputs.

19, 20

FCO−, FCO+

Frame Clock Outputs.

21, 22

D1−B, D1+B

Channel B Digital Outputs.

23, 24

D0−B, D0+B

Channel B Digital Outputs, (Channel A Digital Outputs in One-Lane Mode1).

25, 26

D1−A, D1+A

Channel A Digital Outputs, (Disabled in One-Lane Mode1).

27, 28

D0−A, D0+A

Channel A Digital Outputs, (Disabled in One-Lane Mode1).

SCLK/DTP

SPI Clock Input/Digital Test Pattern.

SDIO/OLM

SPI Data Input and Output Bidirectional SPI Data/Output Lane Mode.

CSB

SPI Chip Select Bar. Active low enable; 30 kΩ internal pull-up.

PDWN

Digital Input, 30 kΩ Internal Pull-Down.

PDWN high = power-down device.

PDWN low = run device, normal operation.

VIN−A

ADC A Analog Input Complement.

VIN+A

ADC A Analog Input True.

VIN+B

ADC B Analog Input True.

VIN−B

ADC B Analog Input Complement.

RBIAS

Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.

SENSE

Reference Mode Selection.

VREF

Voltage Reference Input and Output.

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