AD9683 datasheet(43/45 Pages) AD

43 / 45 page

AD9683

Data Sheet

Rev. D | Page 42 of 44

JESD204B Checksum (Address 0x79)

Bits[7:0]—JESD204B checksum value for the output lane

This read only register is automatically calculated for the lane.

Checksum equals sum (all link configuration parameters for the

lane) modulus 256.

JESD204B Output Driver Control (Address 0x80)

Bits[7:1]—Reserved

Bit 1—JESD204B driver power-down

When this bit is set low, the JESD204B output drivers are enabled.

When this bit is set high, the JESD204B output drivers are

powered down.

JESD204B LMFC Offset (Address 0x8B)

Bits[7:5]—Reserved

Bits[4:0]—Local multiframe clock phase offset value

These bits are the reset value for the local multiframe clock

(LMFC) phase counter when SYSREF± is asserted. These bits

are used in applications requiring deterministic delay.

JESD204B Preemphasis (Address 0xA8)

Bits[7:0]—JESD204B preemphasis enable option

These bits enable the preemphasis feature on the JESD204B

output drivers. Setting Bits[7:0] to 0x04 disables premphasis,

and setting Bits[7:0] to 0x14 enables preemphasis.

AD9683 데이터시트(PDF) 43 Page - Analog Devices