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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AD6650PCB 데이터시트(PDF) 6 Page - Analog Devices |
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AD6650PCB 데이터시트(HTML) 6 Page - Analog Devices |
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6 / 28 page  Preliminary Technical Data AD6650 REV. PrJ 02/27/2003 6 GENERAL TIMING CHARACTERISTICS Parameter (Conditions) Temp Test Level Min AD6650 Typ Max Units CLK Timing Requirements: tCLK CLK Period Full I 9.6 ns tCLKL CLK Width Low Full IV 0.5 x tCLK ns tCLKH CLK Width High Full IV 0.5 x tCLK ns /RESET Timing Requirements: tRESL /RESET Width Low Full IV 30 ns SYNC Timing Requirements: tSS SYNC to ↑CLK Setup Time Full IV ns tHS SYNC to ↑CLK Hold Time Full IV ns Master Mode Serial Port Timing Requirements (SBM=1): Switching Characteristics2 tDSCLK1 ↑CLK to ↑SCLK Delay (divide by 1) Full IV 3.9 13.4 ns tDSCLKH ↑CLK to ↑SCLK Delay (for any other divisor) Full IV 4.4 14.0 ns tDSCLKL ↑CLK to ↓SCLK Delay (divide by 2 or even #) Full IV 3.25 6.7 ns tDSCLKLL ↓CLK to ↓SCLK Delay (divide by 3 or odd #) Full IV 3.8 6.9 ns tDSDFS ↑SCLK to SDFS Delay Full IV 3.02 ns tDSDO ↑SCLK to SDO Delay Full IV 2.7 ns tDSD1 ↑SCLK to SD1 Delay Full IV 2.6 ns tDSDR ↑SCLK to DR Delay Full IV 2.7 ns Slave Mode Serial Port Timing Requirements (SBM=0): Switching Characteristics2 tSCLK SCLK Period Full IV 16.0 ns tSCLKL SCLK low time (when SDIV=1, divide by 1) Full IV 5.0 ns tSCLKH SCLK high time (when SDIV=1, divide by 1) Full IV 5.0 ns tDSDO ↑SCLK to SDO Delay Full IV 6.8 ns tDSD1 ↑SCLK to SD1 Delay Full IV 6.8 ns t DSDR ↑SCLK to DR Delay Full IV 6.9 ns Input Characteristics tSSF SDFS to ↑SCLK Setup Time Full IV 2.6 ns tHSF SDFS to ↑SCLK Hold Time Full IV -1.15 ns 1All Timing Specifications valid over VDD range of 3.0V to 3.6V and VDDIO range of 3.0V to 3.6V. 2The timing parameters for SCLK, SDFS, SDO0, SDO1, and DR apply to both channels (0, 1). The Slave serial port’s (SCLK) operating frequency is limited to 52 MHz. 3Specification pertains to control signals: RW, (/WR), /DS, (/RD), /CS 4(CLOAD=40pF on all outputs unless otherwise specified) |
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