AD5171

For log taper adjustment, such as volume control, Figure 45

shows another way of resistance scaling to achieve the log taper

the more like the pseudo log taper characteristic it behaves. The

wiper voltage is simply

I

WB

WA

WB

W

V

R

R

R

R

R

D

V

×

+

=

2

||

)

2

||

(

)

(

(6)

R1

B

A

R2

W

Figure 45. Resistor Scaling with Log Adjustment Characteristics

RESOLUTION ENHANCEMENT

The resolution can be doubled in the potentiometer mode of

operation by using three digital potentiometers. Borrowed from

ADI’s patented RDAC segmentation technique, users can con-

figure three AD5171 (Figure 46) to double the resolution. First,

adjusting U1 and U2 together forms the coarse 6-bit adjustment

and that adjusting U3 alone forms the finer 6-bit adjustment. As a

result, the effective resolution becomes 12-bit.

U1

A1

B1

W1

U2

A2

B2

W3

W2

U3

A3

B3

COARSE

ADJUSTMENT

FINE

ADJUSTMENT

Figure 46. Doubling the Resolution

RDAC CIRCUIT SIMULATION MODEL

The internal parasitic capacitances and the external capacitive

loads dominate the ac characteristics of the digital potentio-

meters. Configured as a potentiometer divider, the –3 dB

bandwidth of the AD5171 (5 kΩ resistor) measures 1.5 MHz at

half scale. Figure 14 to Figure 17 provide the large signal BODE

plot characteristics of the four available resistor versions 5 kΩ

10 kΩ, 50 kΩ, and 100 kΩ. A parasitic simulation model is

shown in Figure 47. Listing 1 provides a macro model net list

for the 10 kΩ device.

55pF

25pF

25pF

A

B

RDAC

10k

Ω

W

Figure 47. Circuit Simulation Model for RDAC = 10 kΩ

Listing 1. Macro Model Net List for RDAC

.PARAM D=64, RDAC=10E3

*

.SUBCKT DPOT (A,W,B)

*

CA

A

0

25E-12

RWA

A

W

{(1-D/64)*RDAC+60}

CW

W

0

55E-12

RWB

W

B

{D/64*RDAC+60}

CB

B

0

25E-12

*

.ENDS DPOT

Rev. PrC | Page 18 of 20

Preliminary Technical Data