CDCU877/CDCU877A

1.8V PHASE LOCK LOOP CLOCK DRIVER

SCAS688A − JUNE 2003 − REVISED JANUARY 2004

12

POST OFFICE BOX 655303

V

DDQ

GND

CARD

VIA

CARD

VIA

Bead

0603

4.7 uF

1206

0.1 uF

0603

2200 pF

0603

AV

DD

AGN D

PLL

See Notes 9, 10, and 11

1 Ohm

NOTES:

9. Place the 2200-pF capacitor close to the PLL.

10. Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connect trace to one GND

via (farthest from the PLL).

11. Recommended bead: Fair-Rite PN 2506036017Y0 or equilvalent (0.8

Ω dc maximum, 600 Ω at 100 MHz).