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AT40K 데이터시트(PDF) 28 Page - ATMEL Corporation

부품명 AT40K
상세설명  5K - 50K Gates Coprocessor FPGA with FreeRAM
PDF  67 Pages
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제조업체  ATMEL [ATMEL Corporation]
홈페이지  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT40K 데이터시트(HTML) 28 Page - ATMEL Corporation

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AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AC Timing Characteristics – 5V Operation AT40K
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 4.75V, temperature = 70°C
Minimum times based on best case: VCC = 5.25V, temperature = 0°C
Maximum delays are the average of tPDLH and tPDHL.
Cell Function
Parameter
Path
-2
Units
Notes
Async RAM
Write
tWECYC (Minimum)
cycle time
8.0
ns
Write
t
WEL (Minimum)
we
3.0
ns
Pulse width low
Write
t
WEH (Minimum)
we
3.0
ns
Pulse width high
Write
t
AWS (Minimum)
wr addr setup -> we
2.0
ns
Write
tAWH (Minimum)
wr addr hold -> we
0.0
ns
Write
tDS (Minimum)
din setup -> we
2.0
ns
Write
tDH (Minimum)
din hold -> we
0.0
ns
Write/Read
t
DD (Maximum)
din -> dout
4.6
ns
rd addr = wr addr
Read
t
AD (Maximum)
rd addr -> dout
3.1
ns
Read
t
OZX (Maximum)
oe -> dout
1.6
ns
Read
tOXZ (Maximum)
oe -> dout
2.0
ns
Sync RAM
Write
tCYC (Minimum)
cycle time
8.0
ns
Write
t
CLKL (Minimum)
clk
3.0
ns
Pulse width low
Write
t
CLKH (Minimum)
clk
3.0
ns
Pulse width high
Write
t
WCS (Minimum)
we setup -> clk
2.0
ns
Write
tWCH (Minimum)
we hold -> clk
0.0
ns
Write
tACS (Minimum)
wr addr setup -> clk
2.0
ns
Write
tACH (Minimum)
wr addr hold -> clk
0.0
ns
Write
tDCS (Minimum)
wr data setup -> clk
2.0
ns
Write
t
DCH (Minimum)
wr data hold -> clk
0.0
ns
Write/Read
t
CD (Maximum)
clk -> dout
3.5
ns
rd addr = wr addr
Read
tAD (Maximum)
rd addr -> dout
3.1
ns
Read
tOZX (Maximum)
oe -> dout
1.6
ns
Read
tOXZ (Maximum)
oe -> dout
2.0
ns



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