AD9444-CMOSSLASHPCB datasheet(40/41 Pages) AD

40 / 41 page

AD9444

Rev. 0 | Page 39 of 40

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MS-026AED-HD

NOTES

1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.

2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF

THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF

THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL

TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE

SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE

DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.

3. THE EXPOSED HEAT SINK SOLDERED TO THE GROUND PLANE IS REQUIRED FOR THE 100-LEAD TQFP/EP.

100

14.00 SQ

16.00 SQ

0.27

0.22

0.17

0.50 BSC

1.05

1.00

0.95

0.15

0.05

0.75

0.60

0.45

SEATING

PLANE

1.20

MAX

100

6.50

NOM

7°

3.5°

0°

COPLANARITY

0.08

0.20

0.09

TOP VIEW

(PINS DOWN)

BOTTOM VIEW

(PINS UP)

CONDUCTIVE

HEAT SINK

Figure 70. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

(SV-100-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Outline

AD9444BSVZ-801

–40°C to +85°C

100-Lead TQFP_EP

SV-100-1

AD9444-CMOS/PCB

CMOS Mode Evaluation Board

AD9444-LVDS/PCB

LVDS Mode Evaluation Board

1 Z = Pb-free part.

AD9444-CMOS/PCB 데이터시트(PDF) 40 Page - Analog Devices

AD9444-CMOS/PCB 데이터시트(HTML) 40 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

데이터시트 다운로드

링크 URL