data in the ASIC thus avoiding the use of the CLK signal

altogether. However, since the ABb signal edges are pro-

vided in-phase with the data transitions, generally the ASIC

circuitry would have to delay the ABb signal with respect to

the data in order to use it as the clock for the capturing

latches. It is also possible to use the CLK signal to latch the

data in the multiplexed mode as well - as described in the

previous paragraph.

Be very careful when driving a high capacitance bus. The

more capacitance the output drivers must charge for each

conversion, the more instantaneous digital current flows

through V

spikes can cause on-chip ground noise and couple into the

analog circuitry, degrading dynamic performance. Adequate

bypassing, limiting output capacitance and careful attention

to the ground plane will reduce this problem. Additionally,

bus capacitance beyond the specified 15 pF/pin will cause

t

output data. The result could be an apparent reduction in

dynamic performance.

To minimize noise due to output switching, minimize the load

currents at the digital outputs. This can be done by connect-

ing buffers (74ACQ541, for example) between the ADC out-

puts and any other circuitry. Only one driven input should be

connected to each output pin. Additionally, inserting series

resistors of about 100

Ω at the digital outputs, close to the

ADC pins, will isolate the outputs from trace and other circuit

capacitances and limit the output currents, which could oth-

erwise result in performance degradation. See Figure 4.

20100213

FIGURE 4. Application Circuit using Transformer or Differential Op-Amp Drive Circuit, Parallel mode

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