AD9200ARS datasheet(4/25 Pages) AD

4 / 25 page

Parameter

Symbol

Min

Typ

Max

Units

Condition

DIGITAL INPUTS

High Input Voltage

VIH

2.4

Low Input Voltage

VIL

0.3

DIGITAL OUTPUTS

High-Z Leakage

IOZ

–10

+10

µA

Output = GND to VDD

Data Valid Delay

tOD

CL = 20 pF

Data Enable Delay

tDEN

Data High-Z Delay

tDHZ

LOGIC OUTPUT (with DRVDD = 3 V)

High Level Output Voltage (IOH = 50 µA)

VOH

+2.95

High Level Output Voltage (IOH = 0.5 mA)

VOH

+2.80

Low Level Output Voltage (IOL = 1.6 mA)

VOL

+0.4

Low Level Output Voltage (IOL = 50 µA)

VOL

+0.05

LOGIC OUTPUT (with DRVDD = 5 V)

High Level Output Voltage (IOH = 50 µA)

VOH

+4.5

High Level Output Voltage (IOH = 0.5 mA)

VOH

+2.4

Low Level Output Voltage (IOL = 1.6 mA)

VOL

+0.4

Low Level Output Voltage (IOL = 50 µA)

VOL

+0.1

CLOCKING

Clock Pulsewidth High

tCH

22.5

Clock Pulsewidth Low

tCL

22.5

Pipeline Latency

Cycles

CLAMP

Clamp Error Voltage

EOC

±20

±40

CLAMPIN = 0.5 V–2.7 V, RIN = 10 Ω

Clamp Pulsewidth

tCPW

µsC

IN = 1 µF (Period = 63.5 µs)

NOTES

1See Figures 1a and 1b.

2Available only in AD9200ARS and AD9200KST.

Specifications subject to change without notice.

AD9200

REFTS

REFBS

MODE

AVDD

10k

0.4

VDD

AD9200

REFTS

REFBF

MODE

REFTF

REFBS

4.2k

Figure 1a.

Figure 1b.

AD9200

–3–

REV. E

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