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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADAU1772BCPZ-R7 데이터시트(PDF) 12 Page - Analog Devices |
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ADAU1772BCPZ-R7 데이터시트(HTML) 12 Page - Analog Devices |
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12 / 117 page  Data Sheet ADAU1772 Rev. C | Page 11 of 116 Limit Parameter TMIN TMAX Unit Description DIGITAL MICROPHONE tCF 20 ns Digital microphone clock fall time tCR 20 ns Digital microphone clock rise time tDS 40 Digital microphone valid data start time tDE 0 ns Digital microphone valid data end time PDM OUTPUT tDCF 20 ns PDM clock fall time tDCR 20 ns PDM clock rise time tDDV 0 30 ns PDM delay time for valid data Digital Timing Diagrams Figure 2. Serial Input Port Timing BCLK LRCLK DAC_SDATA LEFT-JUSTIFIED MODE LSB DAC_SDATA I2S MODE DAC_SDATA RIGHT-JUSTIFIED MODE tBH MSB MSB – 1 MSB MSB 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) tLS tSS tSH tSH tSS tSS tSH tSS tSH tLH tBL |
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