SSM2604 datasheet(16/29 Pages) AD

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Data Sheet

SSM2604

Rev. A | Page 15 of 28

SOFTWARE CONTROL INTERFACE

The software control interface provides access to the user-

selectable control registers and can operate with a 2-wire (I2C®)

interface.

Within each control register is a control data-word consisting

of 16 bits, MSB first. Bit D15 to Bit D9 are the register map

address, and Bit D8 to Bit D0 are register data for the associated

SDIN generates the serial control data-word; SCLK clocks the

serial data,

The device address for the SSM2604 is 0011010.

CONTROL REGISTER SEQUENCING

1. Enable all of the necessary power management bits of

out bit should be set to 1 until the final step of the control

2. After the power management bits are set, program all other

necessary registers, with the exception of the active bit

[Register R9, Bit D0] and the out bit of the power

management register.

3. As described in the Digital Core section of the Theory of

Operation, insert enough delay time to charge the VMID

decoupling capacitor before setting the active bit [Register

R9, Bit D0].

4. Finally, to enable the DAC output path of the SSM2603, set

the out bit of Register R6 to 0.

1 TO 7

SDIN

SCLK

START

ADDR

R/W

ACK

SUBADDRESS

ACK

STOP

DATA

Figure 24. 2-Wire I2C Generalized Clocking Diagram

WRITE

SEQUENCE

READ

SEQUENCE

SA1

A(S)

D15

...

A(S)

...

A(M)

...

DEVICE

ADDRESS

DEVICE

ADDRESS

SA1

A(S)

D15

...

DEVICE

ADDRESS

DATA

(SLAVE DRIVE)

DATA

S/P = START/STOP BIT.

A0 = I2C R/W BIT.

A(S) = ACKNOWLEDGE BY SLAVE.

A(M) = ACKNOWLEDGE BY MASTER.

A(M) = ACKNOWLEDGE BY MASTER (INVERSION).

Figure 25. I2C Write and Read Sequences

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