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PECL_RX 데이터시트(PDF) 4 Page - ams AG |
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PECL_RX 데이터시트(HTML) 4 Page - ams AG |
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4 / 6 page ![]() Datasheet: PECL_RX - C35 Revision B, 10.09.02 Page4of6 SYMBOL OF PECL_RX XPD VINP VINN VOUTP VOUTN High High Low High Low High Low High Low High Low X X High Low PIN LIST OF PECL_RX Pin Description Type VDDPECL Positive Supply for PECL Receiver Supply VDDA Positive Supply Supply VDDCMOS Positive Supply for CMOS Output Buffer Supply VSSPECL Negative Supply Supply VSSCMOS Negative Supply Supply IREFP Bias Current Analog IREFN Bias Current Analog VMID Voltage Reference Analog XPD Power Down Digital SIM Test Pin Digital VINP Positive Input Analog VINN Negative Input Analog VOUTP Pos. PECL Output Digital VOUTN Neg. PECL Output Digital SYMBOL OF PERXBIAS PIN LIST OF PERXBIAS Pin Description Type VDDA Positive Supply Supply VSSA Negative Supply Supply IREFP1 Bias Current Analog IREFP2 Bias Current Analog IREFP3 Bias Current Analog IREFN1 Bias Current Analog IREFN2 Bias Current Analog IREFN3 Bias Current Analog VMID Voltage Reference Analog XSIM Test Pin Digital VREF External Reference Voltage Analog THEORY OF OPERATION The PECL_RX is a differential line receiver which accepts low voltage input signals according to F100K standard. The input signal lines must be 50 Ω transmission lines. At the receiver input each signal has to be terminated to the voltage level VT (where VT = VDDPECL – 2 V) with an external termination resistor of 50 Ω, but also other termination schemes are possible. The cell PECL_RX can be set in power down mode. It requires the PERXBIAS cell for biasing. PERXBIAS can drive up to 3 PECL_RX cells. An external voltage reference must be used. |
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