Philips Semiconductors

Product specification

SCN2652/SCN68652

Multi-protocol communications controller (MPCC)

1995 May 01

18

CLOCK

tCLK1

1/f

TxC

TxSO

tCLK0

TxD

RxC

RxSI

tCLK0

tCLK1

tRxS

tRxH

SD00066

Figure 11. Timing Diagrams (cont.)

TRANSMIT – START OF MESSAGE

TxC

SYNC/FLAG1

1ST CHAR

8 TxC1

MARK

TxSO

TxBE

DBEN

SET TSOM

LOAD 1st CHAR

RESET TSOM

LOAD 2nd CHAR

TxE

TxA

2

3

NOTES:

1.

SYNC may be 5 to 8 bits and will contain parity bit as specified.

2.

TxA goes high relative to TxC rising edge after TSOM has been set and TxE has been raised.

3.

TxBE goes low relative to DBEN falling edge on the first write transfer into TDSR. It is reasserted 1 TxC time before the first bit of the transmitted SYNC/FLAG. TxBE then goes

character, except in BOP mode when the CRC is to be sent as the next character (see Transmit Timing–End of Message).

SD00067

Figure 12. Timing Diagrams (cont.)