| 전자부품 데이터시트 검색엔진 |
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TUSB546AI-DCI 데이터시트(PDF) 26 Page - Texas Instruments |
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TUSB546AI-DCI 데이터시트(HTML) 26 Page - Texas Instruments |
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26 / 49 page ![]() 26 TUSB546A-DCI SLLSF14 – JUNE 2017 www.ti.com Product Folder Links: TUSB546A-DCI Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000] Figure 23. DisplayPort Control/Status Registers (0x13) 7 6 5 4 3 2 1 0 AUX_SNOOP_ DISABLE Reserved AUX_SBU_OVR DP3_DISABLE DP2_DISABLE DP1_DISABLE DP0_DISABLE R/W R R/W R/W R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 15. DisplayPort Control/Status Registers (0x13) Bit Field Type Reset Description 7 AUX_SNOOP_DISABLE R/W 0 0 – AUX snoop enabled. (Default) 1 – AUX snoop disabled. 6 Reserved R 0 Reserved 5:4 AUX_SBU_OVR R/W 00 This field overrides the AUXp or AUXn to SBU1 or SBU2 connect and disconnect based on CTL1 and FLIP. Changing this field to 1’b1 will allow traffic to pass through AUX to SBU regardless of the state of CTLSEL1 and FLIPSEL register 00 – AUX to SBU connect/disconnect determined by CTLSEL1 and FLIPSEL (Default) 01 – AUXp -> SBU1 and AUXn -> SBU2 connection always enabled. 10 – AUXp -> SBU2 and AUXn -> SBU1 connection always enabled. 11 – AUX to SBU open. 3 DP3_DISABLE R/W 0 When AUX_SNOOP_DISABLE = 1’b1, this field can be used to enable or disable DP lane 3. When AUX_SNOOP_DISABLE = 1’b0, changes to this field will have no effect on lane 3 functionality. 0 – DP Lane 3 Enabled (default) 1 – DP Lane 3 Disabled. 2 DP2_DISABLE R/W 0 When AUX_SNOOP_DISABLE = 1’b1, this field can be used to enable or disable DP lane 2. When AUX_SNOOP_DISABLE = 1’b0, changes to this field will have no effect on lane 2 functionality. 0 – DP Lane 2 Enabled (default) 1 – DP Lane 2 Disabled. 1 DP1_DISABLE R/W 0 When AUX_SNOOP_DISABLE = 1’b1, this field can be used to enable or disable DP lane 1. When AUX_SNOOP_DISABLE = 1’b0, changes to this field will have no effect on lane 1 functionality. 0 – DP Lane 1 Enabled (default) 1 – DP Lane 1 Disabled. 0 DP0_DISABLE R/W 0 DISABLE. When AUX_SNOOP_DISABLE = 1’b1, this field can be used to enable or disable DP lane 0. When AUX_SNOOP_DISABLE = 1’b0, changes to this field will have no effect on lane 0 functionality. 0 – DP Lane 0 Enabled (default) 1 – DP Lane 0 Disabled. 8.6.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000] Figure 24. USB3.1 Control/Status Registers (0x20) 7 6 5 4 3 2 1 0 EQ2_SEL EQ1_SEL R/W/U R/W/U LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
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