ST92F120JR1Q6 datasheet(53/324 Pages) STMICROELECTRONICS

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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

In addition, the Code Update routine remaps the

interrupts in the TestFlash (ISR = 23h), and config-

ures I/O Ports P5.3 (SOUT0) and and P5.4

(CLKOUT0) as Alternate Functions.

Note: Four interrupt routines are used by the code

update routine: SCI Receiver Error Interrupt rou-

tine (vector in 0010h), SCI address Match Interrupt

routine (vector in 0012h), SCI Receiver Data

Ready Interrupt routine (vector in 0014h) and SCI

Transmitter Buffer Empty Interrupt routine (vector

in 0016h).

Figure 26. Flash in-system Programming

BRGLR - R253

04h

Baud Rate Divider is 4

SICR - R254

83h

Synchronous Mode

SOCR - R255

01h

Value

Notes

TestFlash Code

Start

Initialization

Enable Serial

Interface

Jump to Flash

Main

Code

In-system

prog routine

Flash

virgin ?

Erase sectors

Yes

Load 1st table

of data in RAM

through S.I.

Prog 1st table

of data from

RAM in Flash

Load 2nd table

of data in RAM

through SCI

Inc. Address

Last

Address ?

RET

Yes

Code Update

Routine

Enable DMA

Load in-system

prog routine

in internal RAM

through SCI.

Call in-system

prog routine

HALT

Address

Match

Interrupt

(from SCI)

User

Test

Internal RAM (User Code Example)

SOUT0

= 0 ?

Yes

WFI

Flash

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