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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST92F120JR1Q7 데이터시트(PDF) 309 Page - STMicroelectronics |
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ST92F120JR1Q7 데이터시트(HTML) 309 Page - STMicroelectronics |
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309 / 324 page  309/324 ST92F120 - ELECTRICAL CHARACTERISTICS A/D EXTERNAL TRIGGER TIMING TABLE (VDD = 5V ± 10%, TA = –40°C to +105°C, CLoad = 50pF, fINTCLK = 24MHz, unless otherwise specified) Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period, standard timer prescaler and counter programmed values. The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 24MHz. Legend: Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2; 2*OSCIN period when OSCIN is divided by 2; OSCIN period / PLL factor when the PLL is enabled. n = number of autoscanned channels (1 ≤ n ≤ 8) A/D EXTERNAL TRIGGER TIMING N° Symbol Parameter Value (Note) Unit Formula Min. Max. 1TwLOW External trigger pulse width 1.5 x Tck 62.5 - ns 2TwHIGH External trigger pulse distance 1.5 x Tck 62.5 - ns 3TwEXT External trigger active edges distance 138 x n x Tck n x 5.75 - µs 4TdSTR EXTRG falling edge and first conversion start 0.5 x Tck 1.5 x Tck 20.8 62.5 ns 1 |
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