TLV1543C, TLV1543I, TLV1543M

3.3V 10BIT ANALOGTODIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004

13

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Access Cycle B

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

A/D Conversion

Interval

Initialize

Initialize

MSB

LSB

Previous Conversion Data

MSB

LSB

B3

B2

B1

B0

C3

B9

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Hi-Z State

12

3

4

5

6

7

8

9

10

1

I/O

CLOCK

DATA

OUT

ADDRESS

CS

EOC

(see Note A)

NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock

after CS

↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup

time has elapsed.

Figure 9. Timing for 10-Clock Transfer Using CS

Access Cycle B

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

A/D Conversion

Interval

Initialize

MSB

LSB

Previous Conversion Data

MSB

LSB

B3

B2

B1

B0

C3

B9

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Low Level

12

3

4

5

6

789

10

1

I/O

CLOCK

DATA

OUT

ADDRESS

CS

EOC

Initialize

(see Note A)

Must be High on Power Up

NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock

after CS

↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup

time has elapsed.

Figure 10. Timing for 10-Clock Transfer Not Using CS