AD5228

Rev. 0 | Page 14 of 20

POWER-UP AND POWER-DOWN SEQUENCES

Because of the ESD protection diodes that limit the voltage

compliance at Terminals A, B, and W (Figure 39), it is important

is powered on unintentionally and can affect other parts of the

and PD pins can be logic high or floating, but they should not

be logic low during power-on.

LAYOUT AND POWER SUPPLY BIASING

It is always a good practice to use compact, minimum lead

length layout design. The leads to the input should be as direct

as possible with a minimum conductor length. Ground paths

should have low resistance and low inductance. It is also good

practice to bypass the power supplies with quality capacitors.

Low ESR (equivalent series resistance) 1 µF to 10 µF tantalum

or electrolytic capacitors should be applied at the supplies to

minimize any transient disturbance and to filter low frequency

ripple. Figure 39 illustrates the basic supply bypassing configu-

ration for the AD5228.

+

GND

AD5228

C2

10

µF

C1

0.1

µF

Figure 40. Power Supply Bypassing