ADT7470 datasheet(5/41 Pages) AD

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ADT7470

Data Sheet

Rev. E | Page 4 of 40

SERIAL BUS TIMING SPECIFICATIONS

Table 2.

Parameter1, 2, 3, 4, 5

Min

Typ

Max

Unit

Test Conditions/Comments

SERIAL BUS TIMING

Clock Frequency, fSCLK

400

kHz

See Figure 2

Glitch Immunity, tSW

See Figure 2

Bus Free Time, tBUF

1.3

μs

See Figure 2

Start Setup Time, tSU;STA

600

See Figure 2

Start Hold Time, tHD;STA

600

See Figure 2

SCL Low Time, tLOW

1.3

μs

See Figure 2

SCL High Time, tHIGH

0.6

μs

See Figure 2

SCL, SDA Rise Time, tr

300

See Figure 2

SCL, SDA Fall Time, tf

300

See Figure 2

Data Setup Time, tSU;DAT

100

See Figure 2

Detect Clock Low Timeout, tTIMEOUT

Can be optionally disabled,

via Configuration Register 1

(see Table 6)

1 VDD should never be floated in the presence of SCL/SDA activity. Charge injection can be sufficient to induce approximately 0.6 V on VDD.

2 All voltages are measured with respect to GND, unless otherwise specified.

3 Typical values are at %A = 25°C and represent the most likely parametric norm.

4 Logic inputs accept input high voltages up to 5 V even when the device is operating at supply voltages below 5 V.

5 Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge.

SCL

SDA

tBUF

tHD;STA

tHD;DAT

tHIGH

tSU;DAT

tHD;STA

tSU;STA

tSU;STO

tLOW

Figure 2. Serial Bus Timing Diagram

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