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CS62180 데이터시트(PDF) 4 Page - Cirrus Logic

부품명 CS62180
상세설명  T1 FRAMER
PDF  50 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS62180 데이터시트(HTML) 4 Page - Cirrus Logic

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Notes:15. Average reframe time is the time from the rising edge of RLOS until the rising edge of RMSYNC
which updates the receiver output timing.
16. With error free data.
SWITCHING CHARACTERISTICS - TRANSMITTER
(TA = -40 to 85
°C; VDD = 5V ± 10%; VIH = 2.0V; VIL = 0.8V; Maximum input rise & fall times of 10 ns)
Parameter
Symbol
Min
Typ
Max
Units
TCLK Period
tP
250
648
-
ns
TCLK Pulse Width
tWL, tWH
125
324
-
ns
TCLK Rise & Fall Times
tF, tR
-20
-
ns
TSER, TABCD, TLINK Setup to TCLK Falling
tSTD
50
-
-
ns
TSER, TABCD, TLINK Hold from TCLK Falling
tHTD
50
-
-
ns
TFSYNC, TMSYNC Setup to TCLK Rising
tSTS
-125
-
125
ns
TFSYNC, TMSYNC Pulse Width
tTSP
100
-
-
ns
Propagation Delays
TFSYNC to TMO, TSIGSEL, TSIGFR, TLCLK
tPTS
-
-
75
ns
TCLK Rising to TCHCLK
tPTCH
-
-
75
ns
SWITCHING CHARACTERISTICS - RECEIVER
(TA = -40 to 85
°C; VDD = 5V ± 10%; VIH = 2.0V; VIL = 0.8V; Maximum input rise & fall times of 10 ns)
Parameter
Symbol
Min
Typ
Max
Units
Transition Time, All Outputs
tTTR
-
-
20
ns
RCLK Period
tP
250
648
-
ns
RCLK Pulse Width
tWL, tWH
100
324
-
ns
RCLK Rise & Fall Times
tF, tR
-20
-
ns
RPOS, RNEG Setup to RCLK Falling
tSRD
50
-
-
ns
RPOS, RNEG Hold to RCLK Falling
tHRD
50
-
-
ns
Minimum RST Pulse Width on System Power Up or Restart
tRST
1-
-
µs
Propagation Delays
RCLK to RMSYNC, RFSYNC,RSIGSEL,
RSIGFR, RLCLK, RCHCLK
tPRS
-
-
75
ns
RCLK to RSER, RABCD, RLINK
tPRD
-
-
75
ns
RCLK to RYEL, RCL, RFER, RLOS, RBV
tPRA
-
-
75
ns
Average Reframe Time
(Notes 15 and 16)
193S
RCR.2 = 0
RCR.2 = 1
tRS
-
-
3.75
7.25
-
-
ms
ms
193E
RCR.2 = 0
RCR.2 = 1
tRS
-
-
7.5
14.5
-
-
ms
ms
T1DM
tRS
-
750
-
µs
SLC-96
®
tRS
-6.0
-
ms
CS62180B
4
DS225PP2



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