PC33879EKSLASHR2 datasheet(8/20 Pages) MOTOROLA

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33879

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

DYNAMIC ELECTRICAL CHARACTERISTICS

Characteristics noted under conditions of 3.1 V

≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C unless otherwise noted.

Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.

Characteristic

Symbol

Min

Typ

Max

Units

POWER OUTPUT TIMING

Output Slew Rate Low-Side Configuration (Note 11)

RLOAD = 620 Ω, CL = 200 pF

tSR(rise)

0.1

0.5

1.0

µs

Output Slew Rate Low-Side Configuration (Note 11)

RLOAD = 620 Ω, CL = 200 pF

tSR(fall)

0.1

0.5

1.0

µs

Output Rise Time High-Side Configuration (Note 11)

RLOAD = 620 Ω, CL = 200 pF

tSR(rise)

0.1

0.3

1.0

µs

Output Fall Time High-Side Configuration (Note 11)

RLOAD = 620 Ω, CL = 200 pF

tSR(fall)

0.1

0.3

1.0

µs

Output Turn ON Delay Time, High-Side and Low-Side Configuration

(Note 12)

tDLY(on)

1.0

µs

Output Turn OFF Delay Time, High-Side and Low-Side Configuration

(Note 12)

tDLY(off)

1.0

100

µs

Output Fault Delay Time (Note 13)

tFAULT

100

–

300

µs

Power-ON Reset Delay

Delay Time Required from Rising Edge of EN and VDD to SPI Active

tPOR

100

–

µs

Low-State Duration on VDD or EN for Reset

VDD or EN ≤ 0.2 V

tRESET

100

–

µs

Notes

11.

Output slew rate respectively measured across a 620

Ω resistive load at 10 to 90 percent and 90 to 10 percent voltage points. CL Capacitor

is connected from Drain or Source output to Ground.

12.

Output turn ON and OFF delay time measured from 50 percent rising edge of CS to the beginning of the 10 and 90 percent transition points.

13.

Duration of fault before fault bit is set. Duration between access times must be greater than 300

µs to read faults.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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