AD6677EBZ datasheet(32/48 Pages) AD

32 / 48 page

AD6677

Data Sheet

Rev. C | Page 32 of 48

DC CORRECTION (DCC)

Because the dc offset of the ADC may be significantly larger than

the signal being measured, a dc correction circuit is included to

null the dc offset before measuring the power. The dc correction

circuit can also be switched into the main signal path; however,

this may not be appropriate if the ADC is digitizing a time-varying

signal with significant dc content, such as GSM.

DC CORRECTION BANDWIDTH

The dc correction circuit is a high-pass filter with a programmable

bandwidth (ranging between 0.29 Hz and 2.387 kHz at

245.76 MSPS). The bandwidth is controlled by writing to

the four dc correction bandwidth select bits, located at

Address 0x40, Bits[5:2]. The following equation can be used

to compute the bandwidth value for the dc correction circuit:

DC_Corr_BW = 2−k−14 × fCLK/(2 × π)

where:

k is the 4-bit value programmed in Bits[5:2] of Address 0x40

(values between 0 and 13 are valid for k).

fCLK is the AD6677 ADC sample rate in hertz.

DC CORRECTION READBACK

The current dc correction value can be read back in Address 0x41

and Address 0x42. The dc correction value is a 16-bit value that

can span the entire input range of the ADC.

DC CORRECTION FREEZE

Setting Bit 6 of Address 0x40 freezes the dc correction at the

current state and continues to use the last updated value as the

dc correction value. Clearing this bit restarts dc correction and

adds the currently calculated value to the data.

DC CORRECTION ENABLE BITS

Setting Bit 1 of Address 0x40 enables dc correction for use in

the output data signal path.

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