AD9869BCPZ datasheet(30/37 Pages) AD

30 / 37 page

AD9869

Rev. A | Page 29 of 36

CLKOUT1 is a divided version of the VCO output and can be

set to be a submultiple integer of fDAC (fDAC/2R, where R = 0, 1, 2,

or 3). Because this clock is derived from the same set of dividers

used within the PLL core, it is phase-locked to the dividers such

that its phase relationship relative to the signal appearing at

OSCIN (or RXCLK) can be determined upon power-up. In

addition, this clock has a near 50% duty cycle because it is

derived from the VCO. As a result, CLKOUT1 should be

selected before CLKOUT2 as the primary source for system

clock distribution.

CLKOUT2 is a divided version of the reference frequency, fOSCIN,

and can be set to be a submultiple integer of fOSCIN (fOSCIN/2L,

where L = 0, 1, or 2). With L set to 0, the output of CLKOUT2 is

a delayed version of the signal appearing at OSCIN, exhibiting

the same duty cycle characteristics. With L set to 1 or 2, the output

of CLKOUT2 is a divided version of the OSCIN signal, exhibiting

a near 50% duty cycle, but without having a deterministic phase

relationship relative to CLKOUT1 (or RXCLK).

AD9869BCPZ 데이터시트(PDF) 30 Page - Analog Devices