MSP430A005IPWR datasheet(38/47 Pages) TI

38 / 47 page

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361D − JANUARY 2002 − REVISED AUGUST 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic (continued)

port P3, P3.3, input/output with Schmitt-trigger

P3.3/UCLK0

P3IN.3

Pad Logic

P3OUT.3

P3DIR.3

P3SEL.3

UCLK.0

DCM_UCLK

SYNC

STE

STC

From USART0

UCLK0

To USART0

0: Input

1: Output

NOTE: UART mode:

The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always

an input.

SPI, slave mode:

The clock applied to UCLK0 is used to shift data in and out.

SPI, master mode:

The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).

port P3, P3.4, and P3.5 input/output with Schmitt-trigger

P3IN.x

Module X IN

Pad Logic

P3OUT.x

P3DIR.x

P3SEL.x

Module X OUT

Direction Control

From Module

P3.4/UTXD0

P3.5/URXD0

0: Input

1: Output

x {4,5}

PnSel.x

PnDIR.x

DIRECTION

CONTROL

FROM MODULE

PnOUT.x

MODULE X OUT

PnIN.x

MODULE X IN

P3Sel.4

P3DIR.4

VCC

P3OUT.4

UTXD0†

P3IN.4

Unused

P3Sel.5

P3DIR.5

VSS

P3OUT.5

VSS

P3IN.5

URXD0‡

† Output from USART0 module

‡ Input to USART0 module

MSP430A005IPWR 데이터시트(PDF) 38 Page - Texas Instruments

MSP430A005IPWR 데이터시트(HTML) 38 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

데이터시트 다운로드

링크 URL