WM8768

Production Data

w

PD Rev 4.1 March 2005

30

MASTER MODE SELECT

Control bit MS selects between audio interface Master and Slave Modes. In Master mode LRCLK

and BCLK are outputs and are generated by the WM8768. In Slave mode LRCLK and BCLK are

inputs to WM8768.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0001010

Interface Control

5

MS

0

Audio Interface Master/Slave Mode

select:

0: Slave Mode

1: Master Mode

MASTER MODE LRCLK FREQUENCY SELECT

In Master mode the WM8768 generates LRC and BCLK. These clocks are derived from the master

clock and the ratio of MCLK to LRCK is set by RATE.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0001010

Interface Control

8:6

RATE[2:0]

010

Master Mode MCLK: LRCLK ratio

select:

000: 128fs

001: 192fs

010: 256fs

011: 384fs

100: 512fs

101: 768fs

MUTE PIN DECODE

The MUTE pin can either be used as an output or an input. When used as an input the MUTE pins

action can be controlled by setting the DZFM and DZFM4 bit to select the corresponding DAC for

applying the MUTE to. As an output its meaning is selected by the DZFM and DZFM4 control bits. By

default selecting the MUTE pin to represent if DAC1 has received more than 1024 midrail samples

will cause the MUTE pin to assert a softmute on DAC1. Disabling the decode block will cause any

logical high on the MUTE pin to apply a softmute to all DAC’s. For compatibility with the WM8772

register the MUTE pin decode bit is also found in the ADC control register, which is redundant on this

chip. The OR of these two register bit is taken internally.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0001100

ADC Control

6

MPD

0

MUTE pin decode disable:

0: MUTE pin decode enable

1: MUTE pin decode disable

0001111

DAC4 control

5

MPD

0

MUTE pin decode disable:

0: MUTE pin decode enable

1: MUTE pin decode disable