SCAN90CP02SPX datasheet(10/12 Pages) NSC

10 / 12 page

Design-For-Test (DfT) Features

IEEE 1149.1 SUPPORT

The SCAN90CP02 supports a fully compliant IEEE 1149.1

interface. The Test Access Port (TAP) provides access to

boundary scan cells at each LVTTL I/O on the device for

interconnect testing. The TAP also provides access to the

IEEE 1149.6 test features if AC-coupled interconnects are

used.

Refer to the BSDL file located on National’s website for the

details of the SCAN90CP02 IEEE 1149.1 implementation.

IEEE 1149.6 SUPPORT

AC-coupled differential interconnections on very high speed

(1+ Gbps) data paths are not testable using traditional IEEE

1149.1 techniques. The IEEE 1149.1 structures and meth-

ods are intended to test static (DC-coupled), single ended

networks. It is unable to test dynamic (AC-coupled) digital

networks because the AC-coupling blocks static signals.

The SCAN90CP02 - which is intended for use in up to 1.5

Gbps data paths - has been designed with IEEE 1149.6

support to enable test of AC-coupled interconnects.

FAULT INSERTION

StuckAt is a feature that enables the user to override logic

values on any of the external pins during normal operation.

StuckAt can be thought of as having the same capabilities as

the IEEE-1149.1 EXTEST instruction but on a per pin bases.

Because this feature occurs on a per-pin basis, normal

device operation (mission mode) is possible with the excep-

tion of the desired faults.

For more information on any of these features, refer to

Application Note AN-1313, SCAN90CP02 Design-for-Test

Features.

SCAN90CP02SPX 데이터시트(PDF) 10 Page - National Semiconductor (TI)