AD2S1205

Rev. A | Page 16 of 20

INCREMENTAL ENCODER OUTPUTS

The A, B, and NM incremental encoder emulation outputs are

free running and are valid if the resolver format input signals

applied to the converter are valid.

The AD2S1205 emulates a 1024-line encoder, meaning that, in

terms of the converter resolution, one revolution produces 1024 A

and B pulses. Pulse A leads Pulse B for increasing angular rotation

(clockwise direction). The addition of the DIR output negates

the need for external A and B direction decode logic. The DIR

output indicates the direction of the input rotation and is high

for increasing angular rotation. DIR can be considered an asyn-

chronous output that can make multiple changes in state between

two consecutive LSB update cycles. This occurs when the direction

of the rotation of the input changes but the magnitude of the

rotation is less than 1 LSB.

The north marker pulse is generated as the absolute angular

position passes through zero. The north marker pulse width is

set internally for 90° and is defined relative to the A cycle.

Figure 9 details the relationship between A, B, and NM.

A

B

NM

Figure 9. A, B, and NM Timing for Clockwise Rotation

Unlike incremental encoders, the AD2S1205 encoder output is

not subject to error specifications such as cycle error, eccentricity,

pulse and state width errors, count density, and phase ϕ. The

maximum speed rating (n) of an encoder is calculated from its

lution (PPR).

PPR

f

n

MAX

×

= 60

(9)

The A and B pulses of the AD2S1205 are initiated from the inter-

nal clock frequency, which is exactly half the external CLKIN

frequency. With a nominal CLKIN frequency of 8.192 MHz,

the internal clock frequency is 4.096 MHz. The equivalent

encoder switching frequency is

)

Pulse

1

Updates

4

(

MHz

024

.

1

MHz

096

.

4

4

/

1

=

=

×

(10)

For 12 bits, the PPR is 1024. Therefore, the maximum speed (n)

of the AD2S1205 with a CLKIN of 8.192 MHz is

rpm

000

,

60

1024

000

,

024

,

1

60

=

×

=

n

(11)

To achieve the maximum speed of 75,000 rpm, select an

external CLKIN of 10.24 MHz to produce an internal clock

frequency equal to 5.12 MHz.

This compares favorably with encoder specifications, which

depending on the type of light system used. A 1024-line laser-

based encoder has a maximum speed of 7300 rpm.

The inclusion of A and B outputs allows an AD2S1205 and

resolver-based solution to replace optical encoders directly

without the need to change or upgrade the user’s existing

application software.

SUPPLY SEQUENCING AND RESET

The AD2S1205 requires an external reset signal to hold the

range of 4.5 V to 5.5 V.

The RESET pin must be held low for a minimum of 10 μs after

).

Applying a

Figure 10

RESET signal to the AD2S1205 initializes the output

position to a value of 0x000 (degrees output through the parallel,

serial, and encoder interfaces) and causes LOS to be indicated

(LOT and DOS pins pulled low), as shown in

.

Figure 10

Failure to apply the correct power-up/reset sequence may result

in an incorrect position indication.

After a rising edge on the RESET input, the device must be

) for the

internal circuitry to stabilize and the tracking loop to settle to

Figure 10

SAMPLE

pulse must be applied, which in turn releases the LOT and DOT

pins to the state determined by the fault detection circuitry and

provides valid position data at the parallel and serial outputs.

(Note that if position data is acquired via the encoder outputs,

The RESET pin is then internally pulled up.

RESET

4.75V

VALID

OUTPUT

DATA

SAMPLE

LOT

DOS

Figure 10. Power Supply Sequencing and Reset