Data Sheet

AD650

Rev. E | Page 9 of 20

inequality:

NOISE

S

OS

INT

V

V

A

t

C















V

3

10

1

3

(8)

For example, consider an application calling for a maximum

frequency of 75 kHz, a 0 V to 1 V signal range, and supply

voltages of only ±9 V. The component selection guide of Figure 9

in a one-shot time period of approximately 7 μs. Substituting

the input signal is near zero, 1 mA flows through the integration

capacitor to the switched current sink during the reset phase,

Because the integrator output stage requires approximately 3 V

headroom for proper operation, only 0.5 V margin remains for

integrating extraneous noise on the signal line. A negative noise

pulse at this time could saturate the integrator, causing an error

provides much more noise margin, thereby eliminating this

potential trouble spot.

1MHz

100kHz

10kHz

50

100

1000

INPUT

RESISTOR

16.9k

20k

40.2k

100k

100

20

50

100

1000

ONE SHOT CAPACITOR

1000

INPUT

RESISTOR

16.9k

40.2k

100k

20k