AD9856AST datasheet(28/37 Pages) AD

28 / 37 page

AD9856

Rev. C | Page 27 of 36

At the completion of any communication cycle, the AD9856

serial port controller expects the next eight rising SCLK edges

to be the instruction byte of the next communication cycle.

All data input to the AD9856 is registered on the rising edge

of SCLK. All data is driven out of the AD9856 on the falling

edge of SCLK. Figure 44 through Figure 47 show the general

operation of the AD9856 serial port.

INSTRUCTION BYTE

The instruction byte contains the following information as

shown in Table 7.

Table 7. Instruction Byte Information

MSB

LSB

R/W

R/W—Bit 7 determines whether a read or write data transfer

occurs after the instruction byte write. Logic high indicates a

read operation. Logic zero indicates a write operation.

N1, N0—

Bits 6 and 5 of the instruction byte determine the

number of bytes to be transferred during the data transfer cycle

of the communications cycle. Table 8 shows the decode bits.

Table 8. N1, N0 Decode Bits

Description

Transfer 1 byte

Transfer 2 bytes

Transfer 3 bytes

Transfer 4 bytes

A4, A3, A2, A1, A0—

Bits 4, 3, 2, 1, 0 of the instruction byte

determine which register is accessed during the data transfer

portion of the communications cycle. For multibyte transfers,

this address is the starting byte address. The remaining register

addresses are generated by the AD9856.

SDIO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

Figure 44. Serial Port Writing Timing—Clock Stall Low

DO7

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

DON'T CARE

SDIO

SCLK

SDO

DO6 DO5 DO4 DO3 DO2 DO1

DO0

Figure 45. Three-Wire Serial Port Read Timing—Clock Stall Low

SDIO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

Figure 46. Serial Port Write Timing—Clock Stall High

SDIO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

Figure 47. Two-Wire Serial Port Read Timing—Clock Stall High

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